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H S 3120
D ouble Buffered 12-Bit MD AC
FEA TURES * M onolithic Construction * 12 Bit Resolution * 0.01% Non-Linearity * jup Compatible * 4-Quadrant M ultiplication * Latch-up Protected
Sipex D ata Converter Line
DESCRIPTION The HS 3120 is a precision monolithic 12-bit multiplying DA C with internal two-stage input storage registers for easy interfacing with microprocessor busses. It is packaged in a 28-pin DIP to give high I/O design flexibility. DOUBLE BUFFERED - The input registers are sectioned controls are level-triggered to allow static or dynamic into 3 segments of 4 bits each, all individually operation. addressable. The DA C-register, following the input V ERSA .com TILE OUTPUTS - A total of 5 output lines are registers, is a parallel 12-bit register for holding the provided by the HS 3120 to allow unipolar and DA C data while the input registers are updated. Only bipolar output connection with a minimum of the data held in the DA C register determines the external components. The feedback resistor is analog output value of the converter. internal. The resistor ladder network termination is M ICRO PROCESSOR COM PA TIBLE -- The HS 3120 has externally available, thus eliminating an external been designed for great flexibility in connecting to resistor for the 1 LSB offset in bipolar mode. bus-oriented systems. The 12 data inputs are M ONOLITHIC CM OS CONSTRUCTION - The HS 3120 is organized into 3 independent addressable 4-bit input a one-chip CM OS circuit with a resistor ladder registers such that the HS 3120 can be connected to network designed for 0.01% linearity without laser either a 4, 8 or 16-bit data bus. The control logic of trimming. Small chip size and high manufacturing the HS 3120 includes chip enable and latch enable yields result in greatly reduced cost. inputs for flexible memory mapping. A ll
FUNCTIONA L DIA GRA M
CE HBE M BE LBE LDA C 22 25 24 23 21
(M SB) BIT 1 2 9 10 11
3
4 12
5
6
7
8
9 17
10 18
(LSB) 11 BIT 12 V REF 19 20 4
13 14
15 16
INPUT REGISTER CONTROL LOGIC
INPUT REGISTER
INPUT REGISTER
R
5 6
FB 1 I 01 I 02 FB 4 FB 3
DA C REGISTER
12 BIT M DA C
7 1 R/ 2 R/ 2 3
HS 3120
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28 V DD1 26 V DD2 27 GND 8 GND 2 LDTR
165 Cedar Hill Street, Marlborough, MA 01752 Tel: 508.485.6350 www.satconelectronics.com
Fax: 508.485.5168
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SPECIFICATIO N S
(Typical @ 25C, nominal power supply, VREF=+10V, unipolar unless otherwise noted).
M ODEL TY PE DIGITA L INPUT Resolution 2-Quad. Unipolar Coding 4-Quad. Bipolar Coding Logic Compatibility2 Input Current Data Set-up Time 3 Strobe W idth 3 Data Hold Time 3 REFERENCE INPUT V oltage Range Input Impedance A NA LOG OUTPUT Scale Factor Scale Factor A ccuracy4 Output Leakage 5 @25C @125C Output Capacitance C OUT 1 , all inputs high C OUT 1 , all inputs low C OUT 2 , all inputs high C OUT 2 , all inputs low STA TIC PERFORM A NCE Integral Linearity Differential Linearity M onotonicity M onotonicity Temp. Range C-M odels B-M odels DY NA M IC PERFORM A NCE Digital Small Signal Settling Full Scale Transition Settling to 0.01% (strobed) Reference Feedthrough Error (V Ref=20V pp) @1kHz @10kHz Delay to output from Bits input from LDA C from CE STA BILITY (Over Specified Temp. Range) Scale Factor 4 Integral Linearity Differential Linearity M onotonicity Temp. Range C-Option B-Option POW ER SUPPLY (V DD) Operating V oltage (specifications guaranteed) M aximum V oltage Range Current Rejection Ratio TEM PERA TURE RA NGE Operating C-Option Operating B-Option Storage M ECHA NICA L Case Style C-Option B-Option
HS3120-2 M ULTIPLY ING, DOUBLE BUFFERED INPUTS 12-Bits Binary1 , Comp. Binary1 Offset Binary CM OS, TTL 1 A (max) 250nS (min) 250nS (min) OnS (min) 25V (max) 8k 50% 125A /V Ref 50% 0.4% <10nA (max) <200nA (max) 80pF 40pF 40pF 80pF 0.015% F.S.R. (max) 0.024% F.S.R. (max) Guaranteed to 12 bits 0C to +70C -55C to +125C 1.0sec 2.0sec <1mV 2mV 100nS6 200nS6 120nS6 2 ppm F.S.R./C (max) 0.2 ppm F.S.R./C (max) 0.2 ppm F.S.R./C (max) 0C to +70C -55C to +125C +15V 5% +5V to 16V 2.5mA (max) 0.002% /% (max) 0C to +70C 55C to +125C -65C to +150C 28-pin double DIP ceramic ceramic
HS 3120-0
0.05% F.S.R. (max) 0.097% F.S.R. (max) Guaranteed to 10 bits
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NOTES: * Same as HS 3120-2 1. The input coding is complementary binary if I O2 is used. 2. Digital input voltage must not exceed supply voltage or go below -0.5V . " 0" <0.8V , 2.4V < " 1" V DD 3. A ll strobes are level triggered. See TIM ING DIA GRA M . 4. Using the internal feedback resistor and an external opamp. 5. The output leakage current will create an offset voltage at the external opamps output. It doubles every 10C temperature increase. 6. Delay times are twice the amount shown at TA =+125C
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M ECHA NICA L
TOP V IEW 0.1 (2.54) PIN 1
PIN A SSIGNM ENTS
PIN 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 FUNCTION FB 4 , Feedback Bipolar Operation LDTR, Ladder Termination FB 3 , Feedback Bipolar Operation V REF Reference V oltage Input 1.3 FB 1 , Feedback, Unipolar/Bipolar (33.02) I 01 , Current out into virtual ground I 02 , Current out-complement of I 01 V SS, Ground, A nalog and DA C Register Bit 1,M SB Bit 2 Bit 3 Bit 4 Bit 5 Bit 6 0.17 Bit 7 (4.3) Bit 8 Bit 9 Bit 10 DIM ENSIONS inch Bit 11 (mm) Bit 12 LDA C, Transfers data from input to DA C register CE, Chip Enable, active low LBE, Bit 12 to Bit 9 Enable CONNECTIONS M BE, Bit 8 to Bit 5 Enable Unipolar .com Operation: HBE, Bit 4 to Bit 1 Enable V DD2 , Supply A nalog and DA C Register V SS1 , Ground input latches Bipolar Operation: V DD1 , Supply input latches Grounding: NOTE:
1.4 (35.56)
0.05 (1.27) TY P
0.05 (1.27)
0.610 (15.49)
0.17 (4.3)
0.006 (0.152) 0.01 TY P (0.25)
NOTE: Pins 8 and 27 and pins 26 and 28 must be connected externally.
Connect I 01 and FB 1 Tie I 02 , (Pin 7). FB 3 , (Pin 3), FB 4 , (Pin 1) all to Ground (Pin 8) Connect I 01 , I 02 , FB 1 , FB 3 , FB 4 Tie LDTR to I 02 Connect all GRD to system analog ground and tie this to digital ground. A ll unused input must be grounded
Consult factory for application information.
ORDERING INFORM A TION
M ODEL HS 312000 HS 3120C-2 HS 3120B-0 HS 3120B-2 DESCRIPTION Double Buffered Double Buffered Double Buffered Double Buffered 12-Bit 12-Bit 12-Bit 12-Bit M DA C. M DA C. M DA C. M DA C. Commercial Commercial M IL-STD-883C M IL-STD-883C CA UTION: ESD (Electro-Static Discharge) sensitive device. Permanent damage may occur when unconnected devices are subjected to high energy electrostatic fields. Unused devices must be stored in conductive foam or shunts. Protective foam should be discharged to the destination socket before devices are removed. Devices should be handled at static safe workstations only. Unused digital inputs must be grounded or tied to the logic supply voltage. Unless otherwise noted, the supply voltage at any digital input should never exceed the supply voltage by more than 0.5 volts or go below -0.5 volts. If this condition cannot be maintained, limit input current on digital inputs by using series resistors or contact Hybrid Systems for technical assistance.
Specifications subject to change without notice.
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